Semiconductor memory devices for storing data can be typically categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when they are no longer coupled to their power supplies, whereas nonvolatile memory devices retain their stored data even without supplied power. Thus, nonvolatile memory devices are widely used in applications where the possibility of power supply interruption is present. For example, nonvolatile memory cells are widely used in cellular phones, digital cameras, MP3 players, etc.
One popular type of nonvolatile memory device is made of flash memory cells having stacked gate structures. Each of the stacked gate structures includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked.
Although flash memory cells have been widely used for a number of years, a relatively new type nonvolatile memory cell is being developed that has several advantages over flash cells. Specifically, a nonvolatile memory device including a phase changeable memory cell is being developed, in part, to replace flash type memory cells.
FIG. 1 is an equivalent circuit diagram of a typical phase changeable memory cell. In FIG. 1, a phase changeable memory cell 10 includes a single access transistor TA and a single variable resistor RV. The variable resistor RV includes a bottom electrode, a top electrode and a phase changeable material layer pattern interposed therebetween. The top electrode is electrically connected to a bit line BL. Also, the access transistor TA includes a source region S that is electrically connected to the bottom electrode, a drain region D which is spaced apart from the source region, and a gate electrode G that is disposed over a channel region between the source region S and the drain region D. The gate electrode G and the drain region D are electrically connected to a word line WL and an interconnection line IL, respectively. As a result, the equivalent circuit of the phase changeable memory cell is similar to that of a DRAM cell. However, properties of the phase changeable material are quite different from that of the dielectric layer of the DRAM cell capacitor. Specifically, the phase changeable material has two stable states that change from one to another based on temperature and time. This allows the variable resistor Rv to have a relatively low or relatively high resistance value, dependent on the state of the phase changeable material. Because this resistance value affects the operation of the memory cell, the state of the phase changeable can be determined by sensing the affect of electrical signals applied to the cell.
FIG. 2 is a graph that illustrates a method of writing data into a phase changeable memory cell. The x-axis represents time T, and the y-axis represents temperature TMP that is applied to the phase changeable material.
Referring to FIG. 2, when the phase changeable material layer is heated to a temperature that is higher than its melting temperature Tm and is cooled down rapidly within a quenching time t1, which is shorter than the crystallization time of the phase changeable material, the phase changeable material layer is transformed into an amorphous state (refer to curve {circle around (1)}). On the contrary, when the phase changeable material layer is heated to a temperature that is in a range between the crystallization temperature Tc and the melting temperature Tm for a second duration T2 (longer than the first duration T1) and is cooled down, the phase changeable material layer is transformed into a crystalline state (refer to curve {circle around (2)}).
Here, a resistivity of the phase changeable material layer in the amorphous state is higher than that of the phase changeable material layer in the crystalline state. Thus, it is possible to determine whether the information stored in the memory cell is a logic “1” or a logic “0” by detecting current that flows through the phase changeable material layer in a read operation of the memory cell.
A material that is widely used as a phase changeable material layer is a compound containing germanium Ge, antimony (stibium) Sb and tellurium Te (hereinafter, referred to as a GST layer).
FIG. 3 is a cross-sectional view of a conventional phase changeable memory cell. In that figure, an isolation layer 13 is located at a predetermined region of a semiconductor substrate 11. The isolation layer 13 defines an active region. A source region 17s and a drain region 17d are disposed in the active region and are spaced apart from each other. A word line is coupled to a gate electrode 15, which is disposed across the active region between the source region 17s and the drain region 17d. The gate electrode 15, the source region 17s and the drain region 17d form an access transistor (TA of FIG. 1). The substrate 11 having the access transistor is covered with a first insulating layer 19. An interconnection line 21 is disposed on the first insulating layer 19. The interconnection line 21 is electrically connected to the drain region 17d through a contact hole that penetrates the first insulating layer 19. A second insulating layer 23 covers the interconnection line 21. A heating plug 25 is disposed in the first and second insulating layers 19 and 23. The heating plug 25 is electrically connected to the source region 17s. A phase changeable material layer pattern 27 and a top electrode 29 are sequentially stacked on the second insulating layer 23. A bottom surface of the phase changeable material layer pattern 27 is in contact with the heating plug 25. A third insulating layer 31 is disposed on the second insulating layer 23, and sidewalls of the phase changeable material layer pattern 27 and the top electrode 29 are surrounded by the third insulating layer 31. A bit line 33 is located on the third insulating layer 31 and is in contact with the top electrode 29.
In a write mode, the access transistor Ta is turned on and a large current flows through the heating plug 25. As a result, an interface between the phase changeable material layer pattern 27 and the heating plug 25 is heated up to transform a portion 27a of the phase changeable material layer 27 into either the amorphous state or the crystalline state, dependant on the length of time and amount of current that flows through the heating plug 25, as explained with reference to FIG. 2.
One problem with the conventional phase changeable transistor as shown in FIG. 3 is that it requires a relatively large amount of current to successfully change the state of the phase changeable material in a successful write operation. One solution would be to reduce a diameter D of the heating plug 25. However, there is a limitation in reducing the diameter D of the heating plug 25, because the minimum diameter D is determined by a photolithographic process. That is to say, it is difficult to consistently make the heating plug 25 with a small diameter because of limitations in the present semiconductor processes.
Embodiments of the invention address this and other limitations of the prior art.